The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods for forming a structure that includes vertical-transport field-effect transistors and structures that include vertical-transport field-effect transistors.
Traditional complementary metal-oxide-semiconductor (CMOS) structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each other through the channel. Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate associated with their formation.
Planar field-effect transistors and fin-type field-effect transistors constitute a category of transistor structures in which the direction of gated current in the channel is in a horizontal direction parallel to the substrate surface. In a vertical-transport field-effect transistor, the source and the drain are arranged at the top and bottom of a semiconductor fin or pillar. The direction of the gated current transport in the channel between the source and drain is generally perpendicular (i.e., vertical) to the substrate surface and parallel to the height of the semiconductor fin or pillar.
The gate length of a vertical-transport field-effect transistor may be defined by depositing a thick layer of a gate material that covers the semiconductor fins and then recessing the gate material to a given height relative to the top surface of the semiconductor fins. The etch-back process used to recess the gate material can introduce variations in the gate length among the different vertical-transport field-effect transistors due to, among other factors, etch loading and variations in the grain size of the gate material.